News

Stay up-to-date with the latest happenings.

2025

Oct 2025

Our ISSCC'25 paper about “SHINSAI: Reusable Active TSV-Interposer” was invited to JSSC and was accepted.

SHINSAI (芯斋) is a 586mm2 reusable active TSV interposer with microbump-level programmable interconnect fabric and 512Mb 3D underdeck SRAM memory.

Aug 2025

Our paper about “VLA-driven Manipulator on FPGA” is accepted by A-SSCC 2025 and selected as a Highlight paper.

We will demonstrate the robotic arm driven by our FPGA accelerator at the Demonstration Session. We look forward to seeing you in Korea.

Jul 2025

Our paper about “Pattern-based Rendering Engine for 3DGS” is accepted by ICCAD 2025.

GauRPE is a SW/HW co-design that performs 3DGS rasterization via pattern matching. Looking forward to the presentation in Munich.

May 2025

I became an tenure-track Assistant Professor at Fudan University.

Still focusing on AI chips for Robotics/LLM/.... Welcome to apply for doctoral and master's degrees!

May 2025

Our paper “A 22-nm 109.3-to-249.5-TFLOPS/W Outlier-Aware ...” was accepted by JSSC.

This paper proposes OA-CIM, a 22nm SRAM-based Compute-in-Memory macro for LLMs. It supports mixed-precision (INT4+FP16) MACs optimized for outlier-aware LLM deployment.

Feb 2025

Our 2 papers about “HW/SW-codesign for MoE” are accepted by DAC 2025.

PIMoE proposes a workload offloading strategy for MoE deployment on NPU-PIM heterogeneous systems, while Hydra addresses the load imbalance challenge among MoE experts in multi-chiplet integrated chips.

Feb 2025

Our paper “SHINSAI: A 586mm2 Reusable Active TSV-Interposer ...” appeared on ISSCC 2025.

SHINSAI (芯斋) is a 586mm2 reusable active TSV interposer with microbump-level programmable interconnect fabric and 512Mb 3D underdeck SRAM memory.

2024

Nov 2024

Our paper “A Real-Time Optical-Flow-based SLAM ...” won the Distinguished Design Award on A-SSCC 2024!

We presented and demonstrated Xiliu, an optical-flow-based SLAM accelerator on FPGA. It exploits the similarity and sparsity of optical flow to achieve real-time performance.

Nov 2024

Our paper “GauSPU: 3D Gaussian Splatting Processor ...” appeared on MICRO 2024.

GauSPU is a HW/SW-cooptimized GPU extension aiming to realize real-time pose tracking in 3D Gaussian Spltting-based SLAM systems.

Oct 2024

Our paper “ST-BPTT: a Memory-Efficient BPTT SNN Training ...” appeared on BioCAS 2024.

This work reduces the memory footprint of BPTT-based SNN training by cutting off the back-propagation paths of the timesteps with low significance.

May 2024

Our 2 Compute-in-Memory papers appeared on ISCAS 2024.

We presented two works, a Logarithmic FP CIM macro and a LUT-based CIM macro. The latter, Trident-CIM, was invited to transfer to TCAS-II.

May 2024

Our paper “SLAM-CIM: A Visual SLAM Backend Processor ...” is accepted by JSSC.

We propose SLAM-CIM, a Compute-in-Memory based visual SLAM backend processor for edge robotics. It features SRAM-based FP16 digital CIM macros supporting both MAC and linear solving.