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Our 2 papers about HW/SW-codesign for MoE are accepted by DAC 2025.
Looking forward to the presentation in San Francisco!
I became an assistant professor at Fudan University.
Still focusing on AI chips for Robotics/LLM/.... Welcome to apply for doctoral and master's degrees!
Our paper “A 22-nm 109.3-to-249.5-TFLOPS/W Outlier-Aware ...” was accepted by JSSC.
This paper proposes OA-CIM, a 22nm SRAM-based Compute-in-Memory macro for LLMs. It supports mixed-precision (INT4+FP16) MACs
Our paper “SHINSAI: A 586mm2 Reusable Active TSV-Interposer ...” appeared on ISSCC 2025.
SHINSAI (芯斋) is a 586mm2 reusable active TSV interposer with microbump-level programmable interconnect fabric and 512Mb 3D underdeck SRAM memory.
Our paper “A Real-Time Optical-Flow-based SLAM ...” won the Distinguished Design Award on A-SSCC 2024!
We presented and demonstrated Xiliu, an optical-flow-based SLAM accelerator on FPGA. It exploits the similarity and sparsity of optical flow to achieve real-time performance.
Our paper “GauSPU: 3D Gaussian Splatting Processor ...” appeared on MICRO 2024.
GauSPU is a HW/SW-cooptimized GPU extension aiming to realize real-time pose tracking in 3D Gaussian Spltting-based SLAM systems.
Our paper “ST-BPTT: a Memory-Efficient BPTT SNN Training ...” appeared on BioCAS 2024.
This work reduces the memory footprint of BPTT-based SNN training by cutting off the back-propagation paths of the timesteps with low significance.
Our 2 Compute-in-Memory papers appeared on ISCAS 2024.
We presented two works, a Logarithmic FP CIM macro and a LUT-based CIM macro. The latter, Trident-CIM, was invited to transfer to TCAS-II.
Our paper “SLAM-CIM: A Visual SLAM Backend Processor ...” is accepted by JSSC.
We propose SLAM-CIM, a Compute-in-Memory based visual SLAM backend processor for edge robotics. It features SRAM-based FP16 digital CIM macros supporting both MAC and linear solving.