Site logo of Haozhe's Blog
Haozhe's Blog
HomeBlogTagsNewsPublicationAbout

Hello! I am Haozhe Zhu

I am a dedicated integrated circuit researcher and a tech enthusiast .

I also go by @zhutmost when coding. Catch me on GitHub!

 

Happy reading! 

Latest News

View all 

Stay up-to-date with the latest happenings.

Oct 2025
Oct 2025
Our ISSCC'25 paper about “SHINSAI: Reusable Active TSV-Interposer” was invited to JSSC and was accepted.
SHINSAI (芯斋) is a 586mm2 reusable active TSV interposer with microbump-level programmable interconnect fabric and 512Mb 3D underdeck SRAM memory.
Aug 2025
Aug 2025
Our paper about “VLA-driven Manipulator on FPGA” is accepted by A-SSCC 2025 and selected as a Highlight paper.
We will demonstrate the robotic arm driven by our FPGA accelerator at the Demonstration Session. We look forward to seeing you in Korea.
Jul 2025
Jul 2025
Our paper about “Pattern-based Rendering Engine for 3DGS” is accepted by ICCAD 2025.
GauRPE is a SW/HW co-design that performs 3DGS rasterization via pattern matching. Looking forward to the presentation in Munich.
May 2025
May 2025
I became an tenure-track Assistant Professor at Fudan University.
Still focusing on AI chips for Robotics/LLM/.... Welcome to apply for doctoral and master's degrees!
May 2025
May 2025
Our paper “A 22-nm 109.3-to-249.5-TFLOPS/W Outlier-Aware ...” was accepted by JSSC.
This paper proposes OA-CIM, a 22nm SRAM-based Compute-in-Memory macro for LLMs. It supports mixed-precision (INT4+FP16) MACs optimized for outlier-aware LLM deployment.
Feb 2025
Feb 2025
Our 2 papers about “HW/SW-codesign for MoE” are accepted by DAC 2025.
PIMoE proposes a workload offloading strategy for MoE deployment on NPU-PIM heterogeneous systems, while Hydra addresses the load imbalance challenge among MoE experts in multi-chiplet integrated chips.
Feb 2025
Feb 2025
Our paper “SHINSAI: A 586mm2 Reusable Active TSV-Interposer ...” appeared on ISSCC 2025.
SHINSAI (芯斋) is a 586mm2 reusable active TSV interposer with microbump-level programmable interconnect fabric and 512Mb 3D underdeck SRAM memory.
(ノ>ω<)ノ
Dive into the News archive!
Find More 

Popular tags feature the most widely favored topics.

Paper Lives Matter AI Chip FPGA PYNQ EDA

My digital garden, where I share my thoughts and ideas.

  • Category

    Research

    Published date

    Estimated reading time

    3 min read

    2026 年智能芯片领域会议概览

    # Paper-Lives-Matter# AI-Chip

    为了准确把握每一个学术交流(摸鱼)的机会,本文收集了 2026 年智能芯片领域(固态电路、体系结构等)的相关学术会议的投稿信息,包括召开时间、地点、截稿时间等。

    Read more
  • Category

    Engineering

    Published date

    Estimated reading time

    9 min read

    2021 年 8 月,我写了这个网站上的第一篇博文 EdgeBoard 的 PYNQ 移植,记录了将 Xilinx PYNQ 框架移植到了 Baidu EdgeBoard 上遇到的九九八十一难。一晃 4 年过去了,Xilinx 已经成了 AMD 的一部分,PYNQ 的版本号也从 v2.7 升级到了 v3.1。PYNQ 仍旧是课题组芯片测试最主要的平台,支撑我们完成了许多款芯片的流片后测试与演示工作。近期借项目需要,我重新试图编译了下 PYNQ,不得不说 PYNQ 的软件工程质量有了明显的提高(泪目!),本文用于记录编译过程,以及中间遇到的一些小问题。

  • Category

    Engineering

    Published date

    Estimated reading time

    16 min read

    互联网上关于如何将 Synopsys、Cadence 等 EDA 软件容器化的开源解决方案并不寻常。借实验室新服务器软件部署的机会,我构建了一套以“易用”为核心的 EDA 容器化方案,在尽可能地对普通用户透明无感的同时,将 EDA 全家桶运行在旧版本系统下,同时支持图形界面、用户容器隔离等。

  • Category

    Research

    Published date

    Estimated reading time

    3 min read

    为了准确把握每一个学术交流(摸鱼)的机会,本文收集了 2025 年智能芯片领域(固态电路、体系结构等)的相关学术会议的投稿信息,包括召开时间、地点、截稿时间等。

  • Category

    Research

    Published date

    Estimated reading time

    3 min read

    为了准确把握每一个学术交流(摸鱼)的机会,本文收集了 2024 年智能芯片领域(固态电路、体系结构等)的相关学术会议的投稿信息,包括召开时间、地点、截稿时间等。